Multi-Level Fault Modeling for Transaction-Level Specifications

被引:0
|
作者
Beltrame, Giovanni [1 ]
Bolchini, Cristiana [1 ]
Miele, Antonio [1 ]
机构
[1] European Space Agcy, NL-2200 AG Noordwijk, Netherlands
来源
GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI | 2009年
关键词
Fault Modeling; Soft Error; TLM; System-Level Design;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Fault modeling is a fundamental element for several activities, ranging from off- and on-line testing, to fault tolerance and dependability-aware design. These activities are carried out during various design phases, dealing with specifications at different abstraction levels. Therefore, modeling faults across abstraction levels is of paramount importance to introduce dependability-related issues from the early phases of design. This paper analyzes how faults can be modeled at the different levels of abstraction with respect to Transaction Level Models, and how these models are related across levels. The work focuses on soft errors and aims at providing support to dependability analysis. A case study of a Transaction Level specification of a Network-on-Chip switch is used to evaluate the methodology and its applicability.
引用
收藏
页码:87 / 92
页数:6
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