Soft Error Resilient VLSI Architecture for Signal Processing

被引：0

作者：

Alnajjar, Dawood ^{[1
,2
]}

Ko, Younghun ^{[1
,2
]}

Imagawa, Takashi ^{[2
,3
]}

Hiromoto, Masayuki ^{[2
,3
]}

Mitsuyama, Yukio ^{[1
,2
]}

Hashimoto, Masanori ^{[1
,2
]}

Ochi, Hiroyuki ^{[2
,3
]}

Onoye, Takao ^{[1
,2
]}

机构：

[1] Osaka Univ, Dept Informat Syst Engn, Suita, Osaka 565, Japan

[2] JST CREST, Suita, Osaka 565, Japan

[3] Kyoto Univ, Dept Commun & Comp Engn, Kyoto, Japan

来源：

2009 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS 2009) | 2009年

关键词：

D O I：

10.1109/ISPACS.2009.5383872

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a reliability-configurable coarse-grained reconfigurable array for signal processing, which offers flexible reliability to soft error. A notion of cluster is introduced as a basic element of the proposed reconfigurable array, each of which can select one of four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by a cluster of the reconfigurable array. A fault-tolerance evaluation of Viterbi decoder mapped on the proposed reconfigurable array demonstrates that there is a considerable trade-off between reliability and area overhead.

引用

页码：183 / +

页数：2

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