Moving from exascale to zettascale computing: challenges and techniques

被引:35
作者
Liao, Xiang-ke [1 ]
Lu, Kai [1 ]
Yang, Can-qun [1 ]
Li, Jin-wen [1 ]
Yuan, Yuan [1 ]
Lai, Ming-che [1 ]
Huang, Li-bo [1 ]
Lu, Ping-jing [1 ]
Fang, Jian-bin [1 ]
Ren, Jing [1 ]
Shen, Jie [1 ]
机构
[1] Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China
关键词
High-performance computing; Zettascale; Micro-architectures; Interconnection; Storage system; Manufacturing process; Programming models and environments; MULTI;
D O I
10.1631/FITEE.1800494
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
High-performance computing (HPC) is essential for both traditional and emerging scientific fields, enabling scientific activities to make progress. With the development of high-performance computing, it is foreseeable that exascale computing will be put into practice around 2020. As Moore's law approaches its limit, high-performance computing will face severe challenges when moving from exascale to zettascale, making the next 10 years after 2020 a vital period to develop key HPC techniques. In this study, we discuss the challenges of enabling zettascale computing with respect to both hardware and software. We then present a perspective of future HPC technology evolution and revolution, leading to our main recommendations in support of zettascale computing in the coming future.
引用
收藏
页码:1236 / 1244
页数:9
相关论文
共 24 条
[1]  
[Anonymous], 18 INT C NETW BAS IN
[2]   Big data and extreme-scale computing: Pathways to Convergence-Toward a shaping strategy for a future software and data ecosystem for scientific inquiry [J].
Asch, M. ;
Moore, T. ;
Badia, R. ;
Beck, M. ;
Beckman, P. ;
Bidot, T. ;
Bodin, F. ;
Cappello, F. ;
Choudhary, A. ;
de Supinski, B. ;
Deelman, E. ;
Dongarra, J. ;
Dubey, A. ;
Fox, G. ;
Fu, H. ;
Girona, S. ;
Gropp, W. ;
Heroux, M. ;
Ishikawa, Y. ;
Keahey, K. ;
Keyes, D. ;
Kramer, W. ;
Lavignon, J-F ;
Lu, Y. ;
Matsuoka, S. ;
Mohr, B. ;
Reed, D. ;
Requena, S. ;
Saltz, J. ;
Schulthess, T. ;
Stevens, R. ;
Swany, M. ;
Szalay, A. ;
Tang, W. ;
Varoquaux, G. ;
Vilotte, J-P ;
Wisniewski, R. ;
Xu, Z. ;
Zacharov, I. .
INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS, 2018, 32 (04) :435-479
[3]   Science and Engineering Beyond Moore's Law [J].
Cavin, Ralph K., III ;
Lugli, Paolo ;
Zhirnov, Victor V. .
PROCEEDINGS OF THE IEEE, 2012, 100 :1720-1749
[4]   Programming languages and compiler design for realistic quantum hardware [J].
Chong, Frederic T. ;
Franklin, Diana ;
Martonosi, Margaret .
NATURE, 2017, 549 (7671) :180-187
[5]   A Survey of Parallel Programming Models and Tools in the Multi and Many-Core Era [J].
Diaz, Javier ;
Munoz-Caro, Camelia ;
Nino, Alfonso .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2012, 23 (08) :1369-1386
[6]  
Glosli JN, 2007, ACM IEEE C SUP
[7]   Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks [J].
Jacob, Philip ;
Zia, Aamir ;
Erdogan, Okan ;
Belemjian, Paul M. ;
Kim, Jin-Woo ;
Chu, Michael ;
Kraft, Russell P. ;
McDonald, John F. ;
Bernstein, Kerry .
PROCEEDINGS OF THE IEEE, 2009, 97 (01) :108-122
[8]  
Jeddeloh J, 2012, INT S VLSI TECHN
[9]  
Jianbin Fang, 2011, 2011 International Conference on Parallel Processing, P216, DOI 10.1109/ICPP.2011.45
[10]  
Keeton K, 2015, 5 INT WORKSH RUNT OP