Numerical Simulation of Charge Multiplication in Ultra-Fast Silicon Detectors (UFSD) and Comparison with Experimental Data

In this contribution we present our most recent numerical investigations towards the development of silicon particle detectors able to provide accurate measurements in both space and time (4D tracking). In particular, we discuss the performances of different Low-Gain Avalanche Diode (LGAD) detectors, by presenting comparisons between measurements and TCAD (Technology Computer-Aided Design) simulations, performed on several detectors fabricated by Fondazione Bruno Kessler (FBK, Italy), Centro Nacional de Microelectronica (CNM, Spain) and Hamamatsu Photonics K.K. Japan). To have a satisfactory timing resolution, carriers multiplication in LGAD has to be properly controlled through the implantation of a specific highly-doped p-type layer underneath the n-cathode. This internal multiplication process is so crucial in view of having large output signals for accurate time measurements, that numerical simulation turns out to he one of the main tools in designing LGADs. For this reason, in this paper we present a simulation framework, where the most robust avalanche models Massey, van Overstraeten-de Man and Okuto-Crowell have been tested. Thus, at the end, we propose a reliable designing tool which is highly predictive in the field of research and development of LGADs.