An integrated low-power Binary-PAM based wireless telemetry circuit for implantable cardiac pacemakers

被引:1
作者
Xu, Jiangtao [1 ]
Zhai, Yujian [1 ]
Yang, Yang [1 ]
Zhang, Ruizhi [1 ]
Zhang, Hong [1 ]
机构
[1] Xi An Jiao Tong Univ, Dept Microelect, Xian 710049, Shanxi, Peoples R China
来源
MICROELECTRONICS JOURNAL | 2020年 / 99卷
基金
美国国家科学基金会;
关键词
Telemetry circuit; DMA; Binary PAM; Low power; Cardiac pacemaker;
D O I
10.1016/j.mejo.2020.104747
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A low-power wireless telemetry circuit integrated in an analog front-end (AFE) chip for implantable cardiac pacemakers is presented in this paper. With an on-chip telemetry circuit, the electrocardiogram (ECG) data can be transmitted directly from the AFE chip to a programmer outside the human body. Such a direct-memory-access (DMA) scheme improves data transmission efficiency and saves the overall power consumption. The proposed telemetry system employs a near-field inductive-coupling link with oscillating frequency of 128 kHz and a binary pulse-amplitude-modulation (PAM) strategy to achieve higher reliability. It consumes lower power and reach a longer communication distance when compared to conventional on-off-keying (OOK) modulation method. In order to further reduce the power consumption, pulse width adjustment technique is adopted in the transmitter. Also, edge detection and window detection techniques are employed in the receiver, making it more robust and immune to noise, disturbance and clock skew. The AFE chip is implemented using a 0.35-mu m CMOS technology and the telemetry circuit occupies an active area of 1150umX350 mu m. Measurement results show that the proposed wireless communication circuit can operate under a power supply range of 2.0-2.8 V, and achieves a maximum communication distance of 12 cm with current consumption lower than 26 mu A and bit error rate less than 10(-5).
引用
收藏
页数:9
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