共 50 条
[21]
A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS
[J].
MICROELECTRONICS JOURNAL,
2018, 73
:24-29
[22]
A Low Power SAR ADC Design Based on Segmented Capacitor
[J].
Tianjin Daxue Xuebao (Ziran Kexue yu Gongcheng Jishu Ban)/Journal of Tianjin University Science and Technology,
2017, 50 (08)
:850-855
[23]
A 13.44-Bit Low-Power SAR ADC for Brain-Computer Interface Applications
[J].
APPLIED SCIENCES-BASEL,
2025, 15 (10)
[24]
A Design of Low Power and Small Area 8 bit 200KS/s Synchronous Single-Ended SAR ADC
[J].
2022 37TH INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUITS/SYSTEMS, COMPUTERS AND COMMUNICATIONS (ITC-CSCC 2022),
2022,
:641-643
[26]
Ultra Low Power 12-Bit SAR ADC for Wireless Sensing Applications
[J].
2016 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURES, TECHNOLOGY AND APPLICATIONS (VLSI-SATA),
2016,
[27]
AZIMUTH AMBIGUITY OF MULTI-CHANNEL SAR
[J].
2012 IEEE INTERNATIONAL GEOSCIENCE AND REMOTE SENSING SYMPOSIUM (IGARSS),
2012,
:3807-3810
[28]
Pipelining method for low-power and high-speed SAR ADC design
[J].
Analog Integrated Circuits and Signal Processing,
2016, 87
:353-368
[30]
Low Power SAR ADC Design with Digital Background Calibration Algorithm
[J].
SYMMETRY-BASEL,
2020, 12 (11)
:1-11