共 50 条
- [21] A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS MICROELECTRONICS JOURNAL, 2018, 73 : 24 - 29
- [22] A Low Power SAR ADC Design Based on Segmented Capacitor Yang, Ruixia (yangrx@hebut.edu.cn), 2017, Tianjin University (50): : 850 - 855
- [23] A Design of Low Power and Small Area 8 bit 200KS/s Synchronous Single-Ended SAR ADC 2022 37TH INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUITS/SYSTEMS, COMPUTERS AND COMMUNICATIONS (ITC-CSCC 2022), 2022, : 641 - 643
- [24] A design methodology for SAR ADC optimal redundancy bit IEICE ELECTRONICS EXPRESS, 2014, 11 (10):
- [25] Ultra Low Power 12-Bit SAR ADC for Wireless Sensing Applications 2016 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURES, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2016,
- [26] AZIMUTH AMBIGUITY OF MULTI-CHANNEL SAR 2012 IEEE INTERNATIONAL GEOSCIENCE AND REMOTE SENSING SYMPOSIUM (IGARSS), 2012, : 3807 - 3810
- [27] Pipelining method for low-power and high-speed SAR ADC design Analog Integrated Circuits and Signal Processing, 2016, 87 : 353 - 368
- [29] Low Power SAR ADC Design with Digital Background Calibration Algorithm SYMMETRY-BASEL, 2020, 12 (11): : 1 - 11
- [30] A Low-Power and Performance-Efficient SAR ADC Design PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017), 2017, : 3 - 4