WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment

被引:18
作者
Giorgi, Roberto [1 ]
Mariotti, Gianfranco [1 ]
机构
[1] Univ Siena, Dept Informat Engn & Math, Siena, Italy
来源
WCAE'19: PROCEEDINGS OF THE WORKSHOP ON COMPUTER ARCHITECTURE EDUCATION | 2019年
基金
欧盟地平线“2020”;
关键词
Computer Simulation; Computer Architecture; RISC-V; Processor Pipeline;
D O I
10.1145/3338698.3338894
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
WebRISC-V is a web-based server-side RISC-V assembly language Pipelined Datapath simulation environment, which aims at easing students learning and instructors teaching experience. RISC-V is an open-source Instruction Set Architecture (ISA) that is highly flexible, modular, extensible and royalty free. Because of these reasons, there is an exploding interest both in the industry and academia for the RISC-V. Here, we present the main features of this simulator and how it can be used for a simple exercise in the classroom. This web-based simulator permits the execution of RISC-V user-provided source code on a five-stage pipeline, while displaying the data of registers, memory and the internal state of the pipeline elements. One of the main advantages of WebRISC-V is the immediate availability in the web browser, thanks to its implementation as a server-side script in PHP.
引用
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页数:6
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