A real-time FPGA-embedded faults classification system powered by phasor estimation and supervised learning algorithms

被引：0

作者：

Buendia, Paola ^{[1
]}

Torres, Cristian ^{[1
]}

Paternina, M. R. A. ^{[1
]}

Zamora, A. ^{[2
]}

机构：

[1] Univ Nacl Autonoma Mexico, Mexico City, DF, Mexico

[2] Univ Michoacana, Morelia, Michoacan, Mexico

来源：

2020 52ND NORTH AMERICAN POWER SYMPOSIUM (NAPS) | 2021年

关键词：

Fault classification; digital relays; power system protection; phasor estimation; support vector machine; discrete Fourier transform; TRANSMISSION-LINES; LOCATION; PERFORMANCE; SELECTION;

D O I：

10.1109/NAPS50074.2021.9449698

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

This paper specializes in developing a real-time faults classification system powered by phasor estimation and supervised learning algorithms. The classification system is embedded in a low-cost Field-Programmable Gate Array (FPGA) programmed using VHSIC Hardware Description Language (VHDL) code, exploiting the flexibility in its parallel architecture and real-time execution that imply faster processing speeds than microcontrollers. The phasor estimation is driven by a non-recursive Discrete Fourier Transform (DFT) and the supervised learning-based classifier model is conducted by a Support Vector Machine (SVM). Experimental tests corroborate the system performance and its reliability under different fault conditions.

引用

页数：6

共 26 条

[1] A digital architecture for support vector machines: Theory, algorithm, and FPGA implementation [J].