Testing high-resolution ADCs with low-resolution/accuracy deterministic dynamic element matched DACs

被引：15
|
作者：
Jiang, Hanjun [1 ]
Olleta, Beatriz
Chen, Degang
Geiger, Randall L.
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
[2] Allegro Microsyst Argentina, RA-1429 Buenos Aires, DF, Argentina
[3] Iowa State Univ, Dept Elect & Comp Engn, Ames, IA 50011 USA
来源：
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT | 2007年 / 56卷 / 05期
关键词：
analog-to-digital converter (ADC) testing; differential nonlinearity (DNL); digital-to-analog converter (DAC); dynamic element matching (DEM); integral nonlinearity (INL);
D O I：
10.1109/TIM.2007.903621
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a deterministic dynamic element matching (DDEM) approach, which is applied to low-precision digital-to-analog converters (DACs) to generate uniformly spaced voltage samples for analog-to-digital converter (ADC) testing. Theoretical analysis is provided to show the test performance using this DDEM DAC. Both simulation results and experimental results from a fabricated DDEM DAC are presented to verify the performance. The ADC testing performance, by using an 8-bit DDEM DAC (linearity less than 5 bits without DDEM), is comparable to the best results reported in the literature using on-chip linear ramp generators. The DDEM technique offers great potential for use in both production test and built-in-self-test (BIST) environments.
引用
收藏
页码：1753 / 1762
页数：10
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