A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)

被引：0

作者：

Vratonjic, Milena ^{[1
]}

Ziegler, Matthew ^{[2
]}

Gristede, George D. ^{[2
]}

Zyuban, Victor ^{[2
]}

Mitchell, Thomas ^{[3
]}

Cho, Ee ^{[4
]}

Visweswariah, Chandu ^{[2
]}

Oklobdzija, Vojin C. ^{[5
]}

机构：

[1] Univ Calif Davis, Davis, CA 95616 USA

[2] TJ Watson Res Ctr, IBM, Yorktown Hts, NY USA

[3] Elect Design Automat, IBM, Burlington, VT USA

[4] Elect Design Automat, Poughkeepsie, NY USA

[5] Univ Texas Dallas, Dallas, TX USA

来源：

INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2010年 / 5953卷

关键词：

Low-power; Optimization; DESIGN;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process using state-of-the-art non-linear optimization solvers and fast circuit simulators. Node switching activities and LDC are integrated into the EinsTuner framework as parameter inputs to the FPR, tuning mode. In FPR, mode: the power is minimized using gate width reduction with respect to power properties of the node. The FPR methodology is evaluated on next generation microprocessor circuit designs. Power reduction results are compared with the results from the existing EinsTuner tuning methodology. The results show improvement; in power reduction with the FPR, optimization mode.

引用

页码：307 / +

页数：2