Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor

被引:0
|
作者
Angamuthu, Rathinam [1 ]
Thangavelu, Karthikeyan [1 ]
Kannan, Ramani [1 ]
机构
[1] Paavai Engn Coll, Dept EEE, Namakkal, India
关键词
Multilevel inverter; APO-PWM; induction motor; total harmonic distortion; topology; DC SOURCES; VOLTAGE; TOPOLOGY; DRIVES; CONVERTERS;
D O I
10.5573/JSTS.2016.16.1.058
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.
引用
收藏
页码:58 / 69
页数:12
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