共 50 条
[42]
A novel process-induced strained silicon (PSS) CMOS technology for high-performance applications
[J].
2005 IEEE VLSI-TSA INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY (VLSI-TSA-TECH), PROCEEDINGS OF TECHNICAL PAPERS,
2005,
:25-26
[43]
High-performance low-power smart antenna for smart world applications
[J].
2014 6TH INTERNATIONAL CONGRESS ON ULTRA MODERN TELECOMMUNICATIONS AND CONTROL SYSTEMS AND WORKSHOPS (ICUMT),
2014,
:480-484
[45]
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
[J].
2004 4TH IEEE CONFERENCE ON NANOTECHNOLOGY,
2004,
:3-6
[47]
Ultra low-power CMOS IC using partially-depleted SOI technology
[J].
PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE,
2000,
:57-60
[48]
A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology
[J].
2008 IEEE CSIC SYMPOSIUM,
2008,
:178-+
[49]
HIGH-PERFORMANCE BULK CMOS TECHNOLOGY WITH MILLISECOND ANNEALING AND STRAINED SI
[J].
16TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED THERMAL PROCESSING OF SEMICONDUCTORS - RTP 2008,
2008,
:37-42