共 50 条
[31]
Low-Power High-Performance Logic Style for Low-Voltage CMOS Technologies
[J].
2008 INTERNATIONAL CONFERENCE ON MICROELECTRONICS,
2008,
:280-283
[34]
Partially depleted CMOS SOI technology for low power RF applications
[J].
GAAS 2005: 13TH EUROPEAN GALLIUM ARSENIDE AND OTHER COMPOUND SEMICONDUCTORS APPLICATION SYMPOSIUM, CONFERENCE PROCEEDINGS,
2005,
:101-104
[35]
Low-power high-performance non-binary CMOS arithmetic circuits
[J].
2000 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION,
2000,
:477-486
[36]
Deep-submicron CMOS technologies for low-power and high-performance operation
[J].
Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi),
1996, 79 (11)
:1-9
[37]
Exploring SOI device structures and interconnect architectures for low-power high-performance circuits
[J].
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES,
2002, 149 (04)
:137-145
[38]
Deep-submicron CMOS technologies for low-power and high-performance operation
[J].
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS,
1996, 79 (11)
:1-9
[39]
A Novel, Low-Cost Deep Trench Decoupling Capacitor for High-Performance, Low-Power Bulk CMOS Applications
[J].
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4,
2008,
:1138-1141
[40]
Performance Analysis of ESD Structures in 130 nm CMOS Technology for Low-Power Applications
[J].
2019 29TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA),
2019,
:28-33