Strained SOI technology for high-performance, low-power CMOS applications

被引：0
|
作者：
Takagi, S [1 ]
Mizuno, T [1 ]
Tezuka, T [1 ]
Sugiyama, N [1 ]
Numata, T [1 ]
Usuda, K [1 ]
Moriyama, Y [1 ]
Nakaharai, S [1 ]
Koga, J [1 ]
Tanabe, A [1 ]
Maeda, T [1 ]
机构：
[1] ASET, MIRAI, Kawasaki, Kanagawa, Japan
来源：
2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS | 2003年 / 46卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：376 / +
页数：3
相关论文
共 50 条
  • [1] HMOS-CMOS - A LOW-POWER HIGH-PERFORMANCE TECHNOLOGY
    YU, K
    CHWANG, RJC
    BOHR, MT
    WARKENTIN, PA
    STERN, S
    BERGLUND, CN
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (05) : 454 - 459
  • [2] 0.18 mu m CMOS technology for high-performance, low-power, and RF applications
    Holloway, TC
    Dixit, GA
    Grider, DT
    Ashburn, SP
    Aggarwal, R
    Shih, A
    Zhang, X
    Misium, G
    Esquivel, AL
    Jain, M
    Madan, S
    Breedijk, T
    Singh, A
    Thakar, G
    Shinn, G
    Riemenschneider, B
    OBrien, S
    Frystak, D
    Kittl, J
    Amerasekera, A
    Aur, S
    Nicollian, P
    Aldrich, D
    Eklund, B
    Appel, A
    Bowles, C
    Parrill, T
    1997 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1997, : 13 - 14
  • [3] Vertically integrated SOI circuits for low-power and high-performance applications
    Wei, LQ
    Zhang, RT
    Roy, K
    Chen, ZP
    Janes, DB
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (03) : 351 - 362
  • [4] Double-gate SOI devices for low-power and high-performance applications
    Roy, K
    Mahmoodi, H
    Mukhopadhyay, S
    Ananthan, H
    Bansal, A
    Cakici, T
    19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 445 - 452
  • [5] Double-gate SOI devices for low-power and high-performance applications
    Roy, K
    Mahmoodi, H
    Mukhopadhyay, S
    Ananthan, H
    Bansal, A
    Cakici, T
    ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 217 - 224
  • [6] Stacked strained silicon transistors for low-power high-performance circuit applications
    Ramakrishnan, H.
    Shedabale, S.
    Russell, G.
    Yakovlev, A.
    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 1793 - 1798
  • [7] Extended 90 nm CMOS technology with high manufacturability for high-performance, low-power, RF/analog applications
    Takao, Y
    Nakai, S
    Horiguchi, N
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2003, 39 (01): : 32 - 39
  • [8] A HIGH-PERFORMANCE LOW-POWER CMOS CHANNEL FILTER
    BLACK, WC
    ALLSTOT, DJ
    REED, RA
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (06) : 929 - 938
  • [9] HIGH-PERFORMANCE LOW-POWER CMOS MEMORIES USING SILICON-ON-SAPPHIRE TECHNOLOGY
    BOLEKY, EJ
    MEYER, JE
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (02) : 135 - &
  • [10] Performances of low-voltage, low-power SOI CMOS technology
    Colinge, JP
    1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2, 1997, : 229 - 236
12345