Capacitive Memory Using GLAD Synthesized Annealed SnO2 Nanowires Array as a Dielectric

被引：4

作者：

Chetri, Priyanka ^{[1
]}

Dhar, Jay Chandra ^{[1
]}

机构：

[1] NIT Nagaland, Dept ECE, Dimapur, India

来源：

PROCEEDINGS OF 3RD IEEE CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2022) | 2022年

关键词：

Glancing Angle Deposition; Interface state density; Nanowires; SnO2;

D O I：

10.1109/VLSIDCS53788.2022.9811450

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the fabrication of as-deposited and annealed SnO2 NWs via GLAD (glancing angle deposition) technique. On investigation, the 650 degrees C SnO2 NWs show improvement in its crystallinity. The capacitive behavior of both the device was analyzed by evaluating the capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics for both asdeposited and annealed sample by varying frequencies. The annealed device showed improved capacitive memory with interface trap density (9.7x10(9) eV(-1) cm(-2)), charge storage density of 5.45x10(10) cm(-2) and memory window of ( )similar to 0.89 V at +/- 8V for 1MHz.

引用

收藏

页码：139 / 142

页数：4

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