application specific integrated circuit;
delay lines;
delay lock loop;
time measurements;
D O I:
10.1109/23.757192
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock, The chip uses an asynchronous interpolator system based on a delay-locked Line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-mu m CMOS process with an area of about 77 mm(2). Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps.