Minimizing peak current via opposite-phase clock tree

被引:29
作者
Nieh, YT [1 ]
Huang, SH [1 ]
Hsu, SY [1 ]
机构
[1] Chung Yuan Christian Univ, Dept Elect Engn, Chungli 32023, Taiwan
来源
42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005 | 2005年
关键词
physical design; clock network synthesis; low power;
D O I
10.1109/DAC.2005.193797
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by the clock tree. In this paper, we propose an opposite-phase scheme for peak current reduction. Our basic idea is to divide the clock buffers at each level of the clock tree into two sets: an half of clock buffers operate at the same phase of the clock source, and another half of clock buffers operate at the opposite phase of the clock source. Consequently, our approach can reduce the peak current of the clock tree nearly 50%. Experimental data consistently show that our approach works well in practice.
引用
收藏
页码:182 / 185
页数:4
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