共 6 条
- [1] Clock skew optimization for peak current reduction [J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1997, 16 (2-3): : 117 - 130
- [2] NEVES JL, 1995, IEEE INT SYMP CIRC S, P1576, DOI 10.1109/ISCAS.1995.523708
- [4] Power minimization by clock root gating [J]. ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 249 - 254
- [5] Vittal A, 1996, IEEE IC CAD, P395, DOI 10.1109/ICCAD.1996.569827
- [6] WANG K, 2004, P IEEE ACM DES AUT C, P497