Low-power SRAMs in nanoscale CMOS technologies

被引：15

作者：

Zhang, Kevin ^{[1
]}

Hamzaoglu, Fatih ^{[1
]}

Wang, Yih ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 01期

关键词：

cache; low-power circuits; static random access memory (SRAM);

D O I：

10.1109/TED.2007.911356

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As CMOS technology scaling is advancing beyond 100 nm, it has become increasingly difficult to meet the power and performance goals for various product applications while achieving aggressive area scaling in static random access memory (SRAM) development. This paper addresses many of the most pressing challenges in today's SRAM design from perspectives of both process technology optimization and design innovation. Key process tradeoff and optimization along with the advanced circuit design techniques for power management and low-voltage operation are discussed.

引用

页码：145 / 151

页数：7

共 28 条

[1] A single-Vt low-leakage gated-Ground cache for deep submicron [J].

Agarwal, A ;

Li, H ;

Roy, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (02) :319-328

[2]

[Anonymous], P IEEE ISSCC FEB

[3] A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell [J].

Bai, P ;

Auth, C ;

Balakrishnan, S ;

Bost, M ;

Brain, R ;

Chikarmane, V ;

Heussner, R ;

Hussein, M ;

Hwang, J ;

Ingerly, D ;

James, R ;

Jeong, J ;

Kenyon, C ;

Lee, E ;

Lee, SH ;

Lindert, N ;

Liu, M ;

Ma, Z ;

Marieb, T ;

Murthy, A ;

Nagisetty, R ;

Natarajan, S ;

Neirynck, J ;

Ott, A ;

Parker, C ;

Sebastian, J ;

Shaheed, R ;

Sivakurnar, S ;

Steigerwald, J ;

Tyagi, S ;

Weber, C ;

Woolery, B ;

Yeoh, A ;

Zhang, K ;

Bohr, M .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :657-660

[4] The impact of intrinsic device fluctuations on CMOS SRAM cell stability [J].

Bhavnagarwala, AJ ;

Tang, XH ;

Meindl, JD .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) :658-665

[5] A pico-joule class, 1 GHz, 32 KByte x 64b DSP SRAM with self reverse bias [J].

Bhavnagarwala, AJ ;

Kosonocky, SV ;

Immediato, M ;

Knebel, D ;

Haen, AM .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :251-252

[6]

Clark LT, 2002, ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P7, DOI 10.1109/LPE.2002.1029503

[7] Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors [J].

Ghani, T ;

Mistry, K ;

Packan, P ;

Thompson, S ;

Stettler, M ;

Tyagi, S ;

Bohr, M .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :174-175

[8]

Horowitz M, 2005, INT EL DEVICES MEET, P11

[9]

Jan CH, 2005, INT EL DEVICES MEET, P65

[10] Two orders of magnitude leakage power reduction of low voltage SRAM's by row-by-row dynamic VDD control (RRDV) scheme [J].

Kanda, K ;

Miyazaki, T ;

Sik, MK ;

Kawaguchi, H ;

Sakurai, T .

15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, :381-385

← 1 2 3 →