A Methodology for Automated Design of Embedded Bit-flips Detectors in Post-Silicon Validation

被引:0
|
作者
Taatizadeh, Pouya [1 ]
Nicolici, Nicola [1 ]
机构
[1] McMaster Univ, Dept Elect & Comp Engn, Hamilton, ON L8S 4K1, Canada
来源
2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | 2015年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Post-silicon validation is concerned with detecting design errors that escape to silicon prototypes and need to be fixed before committing to high-volume manufacturing. Electrical errors are particularly difficult to catch during the pre-silicon phase because of the insufficient accuracy of device models, which is often traded-off against simulation time. This challenge is further aggravated by the rising number of voltage domains, especially if subtle errors are excited in unique electrical states. Since these electrically-induced subtle errors most commonly manifest in the logic domain as bit-flips, to the best of our knowledge there are no systematic methods to design embedded hardware monitors for generic logic blocks that can detect bit-flips with low detection latency. Toward this goal, we propose a methodology that relies on design assertions that are ranked based on their potential to detect bit-flips and subsequently mapped into user-constrained embedded hardware monitors with the aim to increase bit-flip coverage estimate.
引用
收藏
页码:73 / 78
页数:6
相关论文
共 50 条
  • [1] Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation
    Taatizadeh, Pouya
    Nicolici, Nicola
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (12) : 2118 - 2130
  • [2] ISTA: An Embedded Architecture for Post-silicon Validation in Processors
    Lei, Ting
    He, Hu
    Sun, Yihe
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 593 - 596
  • [3] On automated trigger event generation in post-silicon validation
    Ko, Ho Fai
    Nicolici, Nicola
    2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1328 - 1331
  • [4] A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation
    Adir, Allon
    Copty, Shady
    Landa, Shimon
    Nahir, Amir
    Shurek, Gil
    Ziv, Avi
    Meissner, Charles
    Schumann, John
    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 1590 - 1595
  • [5] Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs
    Ko, Ho Fai
    Kinsman, Adam B.
    Nicolici, Nicola
    2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 422 - 431
  • [6] A path-based methodology for post-silicon timing validation
    Lee, L
    Wang, LC
    Mak, TM
    Cheng, KT
    ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2004, : 713 - 720
  • [7] A Randomized Methodology for Post-Silicon Validation of CAN and other Communication Modules
    Ghosh, Debabrata
    Subramanian, Ramasamy
    Murthy, Vinay
    2013 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2013, : 886 - 890
  • [8] Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware
    Lee, Yun Kwan
    Nambiar, Vishnu P.
    Goh, Kim Seng
    Anh Tuan Do
    IECON 2020: THE 46TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2020, : 3836 - 3840
  • [9] Interconnection Fabric Design for Tracing Signals in Post-Silicon Validation
    Liu, Xiao
    Xu, Qiang
    DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2009, : 352 - 357
  • [10] Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation
    Daoud, Ehab Anis
    Nicolici, Nicola
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (04) : 559 - 570