Design and Implementation of A Modified High Performance and Low Power CIC Interpolation Filter

被引:0
作者
Liu, Xiaopeng [1 ]
Han, Yan [1 ]
Liang, Guo [1 ]
Wang, Mingyu [1 ]
Liao, Lu [1 ]
机构
[1] Zhejiang Univ, Inst Microelect & Photoelect, Hangzhou 310027, Zhejiang, Peoples R China
来源
2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2011年
关键词
cascaded integral comb (CIC) interpolation filter; interpolator; poly-phase decomposition; low power; DELTA-A/D CONVERTERS; DECIMATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a modified cascaded integral comb (CIC) interpolation filter in order to improve filter characteristics and reduce power consumption at the same time. The modified CIC interpolation filter is a two-stage multiplier-less CIC-based interpolator. The first stage is a cascaded CIC filter whereas the second stage is a cascaded CIC filter and a second-order compensator. In an effort to reduce power consumption, the poly-phase decomposition and no-recursive algorithm is used when the modified filter is implemented. Simulation and synthesis results indicate that the stop-band attenuation is up to 137.7 dB and the pass-band drop is only 0.0003 dB with the filter interpolation factor 16. Working at 50 MHz clock frequency, the filter can reduce the power consumption of 16.78%. This new interpolator is implemented on Altera Cyclone III EP3C10E144C8 FPGA.
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页数:2
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