Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

被引:6
作者
Jarvinen, Okko [1 ]
Kempi, Ilia [1 ]
Unnikrishnan, Vishnu [1 ]
Stadius, Kari [1 ]
Kosunen, Marko [1 ]
Ryynanen, Jussi [1 ]
机构
[1] Aalto Univ, Dept Elect & Nanoengn, Espoo 02150, Finland
来源
IEEE SOLID-STATE CIRCUITS LETTERS | 2022年 / 5卷
关键词
Analog-to-digital converter (ADC); cyclic-coupled ring oscillator (CCRO); digital calibration; finite-impulse response (FIR); least mean-square (LMS); mismatch; time based; time interleaving; timing skew;
D O I
10.1109/LSSC.2022.3145918
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below -60 dBc while running fully in the background. The operation is demonstrated with an 8x TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.
引用
收藏
页码:9 / 12
页数:4
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