Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology

被引:29
作者
Akbar, Ehsan Pour Ali [2 ]
Haghparast, Majid [1 ]
Navi, Keivan [3 ]
机构
[1] Islamic Azad Univ, Shahre Rey Branch, Dept Comp Engn, Tehran, Iran
[2] Islamic Azad Univ, Dept Comp Engn, Dezful, Iran
[3] Shahid Beheshti Univ, Fac Elect & Comp Engn, Tehran, Iran
关键词
Reversible logic; ZS series gates; Reversible array multiplier; Wallace sign multiplier; LOGIC;
D O I
10.1016/j.mejo.2011.05.007
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Today, reversible logic is emerging as an intensely studied research topic, having applications in diverse fields, such as low-power design, optical information processing, and quantum computation. In this paper, we have proposed two reversible Wallace signed multiplier circuits through modified Baugh-Wooley approach, which are much better than the two available counterparts in all the terms. The multiplier is an essential building block for the construction of computational units of quantum computers. Besides, we need signed multiplier circuits for numerous operations. However, only two reversible signed multiplier circuits have been presented so far. In the first proposed architecture, our goals are to decrease the depth of the circuit and to increase the speed of the circuit. In the second proposed circuit, we aimed to improve the quantum cost, garbage outputs, and other parameters. All the proposed circuits are in the nanometric scales and can be used in the design of very complex systems. (C) 2011 Elsevier Ltd. All rights reserved.
引用
收藏
页码:973 / 981
页数:9
相关论文
共 32 条
[1]  
AbuShama E, 1996, PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, P53, DOI 10.1109/MWSCAS.1996.594026
[2]   Synthesis of reversible logic [J].
Agrawal, A ;
Jha, NK .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, :1384-1385
[3]  
[Anonymous], 1980, INT C AUT LANG PROGR
[4]  
[Anonymous], 2008, Am. J. Appl. Sci., DOI DOI 10.3844/AJASSP.2008.282.288
[5]  
[Anonymous], IEEE T COMPUTERS C
[6]   Design of a compact reversible binary coded decimal adder circuit [J].
Babu, HMH ;
Chowdhury, AR .
JOURNAL OF SYSTEMS ARCHITECTURE, 2006, 52 (05) :272-282
[7]   LOGICAL REVERSIBILITY OF COMPUTATION [J].
BENNETT, CH .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1973, 17 (06) :525-532
[8]   Synthesis of Reversible Sequential Elements [J].
Chuang, Min-Lun ;
Wang, Chun-Yao .
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2008, 3 (04)
[9]  
FEYNMAN RP, 1985, OPT NEWS, V11, P11, DOI [10.1364/ON.11.2.000011, DOI 10.1364/ON.11.2.000011]
[10]  
HAGHPARAST M, 2007, J APPL SCI, V7, P3995, DOI DOI 10.3923/JAS.2007.3995.4000