On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

被引：0

作者：

Ker, MD ^{[1
]}

Hsu, KC ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Integrated Circuits & Syst Lab, Inst Elect, Hsinchu, Taiwan

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the, transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-mum CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40mumx20mum can sustain the HBM ESD stress of higher than 7kV.

引用

页码：529 / 532

页数：4

共 36 条

[1] ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
Ker, MD
Chuang, CH
Hsu, KC
Lo, WY
PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2002, : 331 - 336
[2] SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
Ker, MD
Hsu, KC
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2003, 3 (03) : 58 - 68
[3] Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process
Ker, MD
Hsu, KC
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (02) : 397 - 405
[4] ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design
Chen, TY
Ker, MD
2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, : 232 - 235
[5] Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process
Ker, MD
Tseng, TK
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2004, 43 (1A-B): : L33 - L35
[6] Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process
Ker, M.-D. (mdker@ieee.org), 1600, Japan Society of Applied Physics (43):
[7] On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process
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Ker, MD
2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, : 240 - 243
[8] Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
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Hsu, KC
15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, : 229 - 233
[9] Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process
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Chen, TY
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (04) : 1050 - 1057
[10] A novel substrate-triggered ESD protection structure for a Bus Switch IC with on-chip substrate-pump
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Xu, PP
Chen, WS
Hui, J
Liu, PZQ
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1190 - 1193

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