Bit cost scalable technology with punch and plug process for ultra high density flash memory

被引：442

作者：

Tanaka, H. ^{[3
]}

Kido, M. ^{[3
]}

Yahashi, K. ^{[1
,2
]}

Oomura, M. ^{[1
,2
]}

Katsumata, R. ^{[3
]}

Kito, M. ^{[3
]}

Fukuzumi, Y. ^{[3
]}

Sato, M. ^{[3
]}

Nagata, Y. ^{[4
]}

Matsuoka, Y. ^{[3
]}

Iwata, Y. ^{[3
]}

Aochi, H. ^{[3
]}

Nitayama, A. ^{[3
]}

机构：

[1] Ctr Semicond Res & Dev, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

[2] Proc & Mfg Engn Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

[3] Toshiba Co Ltd, Semicond Co, Isogo ku, 8 Shinsugita Cho, Yokohama, Kanagawa 2358522, Japan

[4] Toshiba Informat Syst Japan Corp, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339708

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

引用

页码：14 / +

页数：2