A Novel Trapping/Detrapping Model for Defect Profiling in High-k Materials Using the Two-Pulse Capacitance-Voltage Technique

The continuous reduction of the dimensions of floating-gate-based nonvolatile memories brings the necessity of substituting the current dielectrics with materials of higher dielectric constant (high-k dielectrics). However, most of the high-k materials studied show a large number of electrically active defects, which mitigates their benefit. The study of these defects, or traps, is necessary in order to fully understand the electrical properties of high-k materials. In this paper, the recently introduced two-pulse capacitance-voltage characterization technique is used, together with a newly developed physics-based model, in order to extract the space and energy location of the traps throughout the high-k dielectrics in advanced memories. An accurate agreement between measurements and simulations is achieved. For the first time, it is shown that traps located in the top part of the bandgap of the high-k materials can be probed and their location in space and energy, as well as their density, can be accurately determined.