A memory efficient array architecture for real-time motion estimation

被引：4

作者：

Moshnyaga, VG

Tamaru, K

机构：

来源：

11TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM, PROCEEDINGS | 1997年

关键词：

D O I：

10.1109/IPPS.1997.580838

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new 2-D array architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the architecture ensures feasible solutions for the HDTV picture format with twice lower memory requirements. It features minimal I/O pin count, 100% processor utilization and is quite suitable for VLSI implementation.

引用

页码：28 / 32

页数：5