A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

被引:0
作者
Masood, Sabeen [1 ]
Khan, Shoab Ahmed [1 ]
Hassan, Ali [1 ]
Khalique, Fatima [2 ]
机构
[1] Natl Univ Sci & Technol NUST, Coll Elect & Mech Engn, Dept Comp & Software Engn, Islamabad 44000, Pakistan
[2] Bahria Univ, Dept Comp Sci, Islamabad 44000, Pakistan
关键词
real-time and embedded systems; embedded processors; interfaces; synchronization; interprocessor communication; debugging; testing; PLATFORM; DESIGN;
D O I
10.3390/electronics11182945
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems.
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页数:22
相关论文
共 54 条
[1]   An Empirical Survey-based Study into Industry Practice in Real-time Systems [J].
Akesson, Benny ;
Nasri, Mitra ;
Nelissen, Geoffrey ;
Altmeyer, Sebastian ;
Davis, Robert, I .
2020 IEEE 41ST REAL-TIME SYSTEMS SYMPOSIUM (RTSS), 2020, :3-11
[2]   Requirements-preserving design automation for multiprocessor embedded system applications [J].
Al Maruf, Md ;
Azim, Akramul .
JOURNAL OF AMBIENT INTELLIGENCE AND HUMANIZED COMPUTING, 2021, 12 (01) :821-833
[3]  
Arora H., 2015, P INT C VLSI SYSTEMS, DOI [10.1109/VLSI-SATA.2015.7050470, DOI 10.1109/VLSI-SATA.2015.7050470]
[4]  
Arora S., 2016, INT TEST CONF P, DOI 10.1109/TEST.2016.7805841
[5]  
Association S.I, 2013, INT TECHNOLOGY ROADM
[6]   Model-Level, Platform-Independent Debugging in the Context of the Model-Driven Development of Real-Time Systems [J].
Bagherzadeh, Mojtaba ;
Hili, Nicolas ;
Dingel, Juergen .
ESEC/FSE 2017: PROCEEDINGS OF THE 2017 11TH JOINT MEETING ON FOUNDATIONS OF SOFTWARE ENGINEERING, 2017, :419-430
[7]  
Bandiziol A., 2016, P 39 INT CONV INF CO
[8]  
Baras N., 2019, P 2019 8 INT C MOD C, P1
[9]  
Bergeron J., 2003, Writing Testbenches. Functional Verification of HDL Models, V2nd ed.
[10]  
Bergeron J., 2006, Writing Testbenches using SystemVerilog