MLMIN: A multicore processor and parallel computer network topology for multicast

被引:24
作者
Tutsch, Dietmar [1 ]
Hommel, Guenter [1 ]
机构
[1] Tech Univ Berlin, Inst Comp Engn & Microelect, D-10587 Berlin, Germany
关键词
cost; multicasting; multicore; multistage interconnection networks; network-on-chip; packet size; performance;
D O I
10.1016/j.cor.2007.02.004
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
In future, multicore processors with hundreds of cores will collaborate on a single chip. Then, more advanced network-on-chip (NoC) topologies will be needed than today's shared busses for dual core processors. Multistage interconnection networks, which are already used in parallel computers, seem to be a promising alternative. In this paper, a new network topology is introduced that particularly applies to multicast traffic in multicore systems and parallel computers. Those multilayer multistage interconnection networks are described by defining the main parameters of such a topology. Performance and costs of the new architecture are determined and compared to other network topologies. Network traffic consisting of constant size packets and of varying size packets is investigated. It is shown that all kinds of multicast. traffic particularly benefit from the new topology. (c) 2007 Elsevier Ltd. All rights reserved.
引用
收藏
页码:3807 / 3821
页数:15
相关论文
共 24 条
[1]  
Alderighi M, 2002, FIRST IEEE INTERNATION WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, P302, DOI 10.1109/DELTA.2002.994635
[2]  
[Anonymous], DOMAIN SPECIFIC PROC
[3]   Networks on chips: A new SoC paradigm [J].
Benini, L ;
De Micheli, G .
COMPUTER, 2002, 35 (01) :70-+
[4]   NoC synthesis flow for customized domain specific multiprocessor systems-on-chip [J].
Bertozzi, D ;
Jalabert, A ;
Murali, S ;
Tamhankar, R ;
Stergiou, S ;
Benini, L ;
De Micheli, G .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2005, 16 (02) :113-129
[5]  
Dally WJ, 2001, DES AUT CON, P684, DOI 10.1109/DAC.2001.935594
[6]   VLSI architecture: Past, present, and future [J].
Dally, WJ ;
Lacy, S .
20TH ANNIVERSARY CONFERENCE ON ADVANCED RESEARCH IN VLSI, PROCEEDINGS, 1999, :232-241
[7]  
Ewing GC, 1999, ESM'99 - MODELLING AND SIMULATION: A TOOL FOR THE NEXT MILLENNIUM, VOL 1, P175
[8]  
Guerrier P., 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), P250, DOI 10.1109/DATE.2000.840047
[9]  
KHALID MA, 1998, P ACM INT S FPGAS, P45
[10]   A UNIFIED THEORY OF INTERCONNECTION NETWORK STRUCTURE [J].
KRUSKAL, CP ;
SNIR, M .
THEORETICAL COMPUTER SCIENCE, 1986, 48 (01) :75-94