A 4-GHz All Digital Fractional-N PLL with Low-Power TDC and Big Phase-Error Compensation

This paper presents an all-digital fractional-N PLL with a low-power TDC operating at the retimed reference clock. Two retimed reference clocks are employed to implement the proposed TDC estimating the fractional phase error between the reference clock and CKV clock. The application of the retimed reference clocks to TDC does not only reduce dynamic power in TDC delay inverter chain, but also simplify epsilon(r) estimation including a new T-v calculation algorithm. Also, phase-error compensation block is presented to compensate for the big phase-error change due to timing skew in the output bits produced from variable-phase counter. And loop settling scanning block is invented to shift DCO operation mode and additionally decrease PLL channel switching time for frequency hopping applications. The proposed all-digital PLL represents -36dBc integrated phase noise (1kHz - 20MHz), 778fs rms jitter, 9.6mW power consumption. The channel switching time of the ADPLL is measured as 630nsec.