Reliability Enhanced SRAM Bit-Cells

Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.