Reliability Enhanced SRAM Bit-Cells

被引：0

作者：

Beiu, Valeriu ^{[1
]}

Tache, Mihai ^{[1
]}

Kharbash, Fekri ^{[1
]}

机构：

[1] United Arab Emirates Univ, Coll Informat Technol, POB 15551, Al Ain, U Arab Emirates

来源：

2014 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS) | 2014年

关键词：

CMOS; SRAM; sizing; SNM; reliability; NOISE MARGIN; DESIGN; LENGTH;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.

引用

页码：229 / 232

页数：4

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