Overview of IP Error Compensation Techniques for EUVL

According to the International Technology Roadmap for Semiconductors, meeting the overlay requirements for the sub-32-nm regime is a difficult challenge for all future lithography technologies. For extreme ultraviolet lithography, the nonflatness of both the mask and chuck contribute to overlay error by way of mask image placement (IP) errors. Consequently it has been proposed to compensate for these IP errors induced during mask fabrication and chucking, by employing correction schemes during the e-beam writing process. This study presents an overview of various IP error compensation techniques currently being considered by the semiconductor industry. Both finite element (FE) and analytical models have been studied and compared to identify the sources of IP errors and the corresponding effects on IP accuracy. Typical examples were used to determine the effects of thin-film deposition and etching, reticle nonflatness, and the chucking process itself. The neutral surface of the mask substrate was tracked via FE modeling and was subsequently used with analytical methods to estimate in-plane distortions. The shortcomings and advantages of implementing these techniques as an e-beam correction strategy are also presented.