Architecture design and hardware implementation of AES encryption algorithm

被引：1
|
作者：
Wei, Hongling [1 ]
Li, Hongyan [1 ]
Chen, Mingying [1 ]
机构：
[1] East Univ Heilongjiang, Dept Mechatron Engn, Harbin, Peoples R China
来源：
2020 5TH INTERNATIONAL CONFERENCE ON MECHANICAL, CONTROL AND COMPUTER ENGINEERING (ICMCCE 2020) | 2020年
关键词：
data encryption; hardware; FPGA; AES;
D O I：
10.1109/ICMCCE51767.2020.00353
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
With the rapid development of the information society, network information security has attracted more attention. Traditional software encryption technology is becoming more and more difficult to ensure people's information security. How to quickly and efficiently ensure people's information security has become one of the key projects studied by scholars. Under this background, this paper designs a simple advanced encryption standard AES FPGA hardware implementation. The content includes the hardware structure design of AES encryption algorithm, comprehensive wiring with Quartus II 13.0, and simulation verification on Modelsim se 10.5.
引用
收藏
页码：1611 / 1614
页数：4
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