A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch

被引:4
|
作者
Yan, Aibin [1 ]
Qian, Kuikui [1 ]
Cui, Jie [1 ]
Cui, Ningning [1 ]
Ni, Tianming [2 ]
Huang, Zhengfeng [3 ]
Wen, Xiaoqing [4 ]
机构
[1] Anhui Univ, Sch Comp Sci & Technol, Hefei, Peoples R China
[2] Anhui Polytech Univ, Coll Elect Engn, Wuhu, Peoples R China
[3] Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei, Peoples R China
[4] Kyushu Inst Technol, Grad Sch Comp Sci & Syst Engn, Fukuoka, Japan
来源
2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH) | 2021年
基金
中国国家自然科学基金;
关键词
Soft error; multiple node upset; triple node upset; self-recoverability; dual-interlocked-storage-cell; AREA-EFFICIENT; SRAM CELLS; DESIGN; TOLERANT; DEVICE;
D O I
10.1109/NANOARCH53687.2021.9642250
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As transistor feature sizes continue to scale down, the susceptibility of integrated circuits to harsh-radiation induced multiple-node-upsets (MNUs),such as double-node upsets (DNUs) and triple-node upsets (TNUs), is increasing. This paper presents an MNU self-recoverable hardened latch (namely SCDMSH) based on sextuple cross-coupled dual-interlocked-storage-cells (DICEs). The latch consists of eight transmission gates and six interlocked DICE cells. Due to the interlocking mechanism constructed from single-node-upset-self-recoverable DICE cells, the latch can self-recover from any possible single node upset (SNU), DNU and TNU. Simulation results validate the SNU, DNU and TNU self-recoverability of the proposed latch. Simulation results also demonstrate that the SCDMSH latch can approximately save 49% silicon area at the cost of moderate delay and power, compared with the state-of-the-art TNU self-recoverable reference latch (TNURL) of the same-type.
引用
收藏
页数:6
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