Sphere decoding for multiprocessor architectures

被引:4
|
作者
Qi, Q. [1 ]
Chakrabarti, C. [1 ]
机构
[1] Arizona State Univ, Dept Elect Engn, Tempe, AZ 85287 USA
来源
2007 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, VOLS 1 AND 2 | 2007年
关键词
sphere decoding; architecture; multiprocessor;
D O I
10.1109/SIPS.2007.4387516
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Motivated by the need for high throughput sphere decoding for multiple input-multiple-output (MIMO) communication systems, we propose a parallel depth-first sphere decoding (PDSD) algorithm that provides the advantages of both parallel processing and rapid search space reduction. The PDSD algorithm is designed for efficient implementation on programmable multi-processor platforms. We investigate the trade-off between the throughput and computation overhead when the number of processing elements is 2, 4 and 8, for a 4 x 4 16-QAM system across a wide range of SNR conditions. Through simulation, we show that PDSD can offer significant throughput improvement without incurring substantial computation overhead by selecting the appropriate number of processing elements according to specific SNR conditions.
引用
收藏
页码:50 / 55
页数:6
相关论文
共 50 条
  • [41] Sphere Decoding for Spatial Modulation
    Younis, Abdelhamid
    Di Renzo, Marco
    Mesleh, Raed
    Haas, Harald
    2011 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), 2011,
  • [42] On the Complexity Distribution of Sphere Decoding
    Seethaler, Dominik
    Jalden, Joakim
    Studer, Christoph
    Boelcskei, Helmut
    IEEE TRANSACTIONS ON INFORMATION THEORY, 2011, 57 (09) : 5754 - 5768
  • [43] Mapping of H.264 decoding on a multiprocessor architecture
    van der Tol, EB
    Jaspers, EGT
    Gelderblom, RH
    IMAGE AND VIDEO COMMUNICATIONS AND PROCESSING 2003, PTS 1 AND 2, 2003, 5022 : 707 - 718
  • [44] Shared memory multiprocessor architectures for software IP routers
    Luo, Y
    Bhuyan, LN
    Chen, X
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2003, 14 (12) : 1240 - 1249
  • [45] COMPARATIVE PERFORMANCE ANALYSIS OF SINGLE BUS MULTIPROCESSOR ARCHITECTURES
    MARSAN, MA
    BALBO, G
    CONTE, G
    IEEE TRANSACTIONS ON COMPUTERS, 1982, 31 (12) : 1179 - 1191
  • [46] Evaluation of Heterogeneous Multiprocessor Architectures by Energy and Performance Optimization
    Orsila, Heikki
    Salminen, Erno
    Hannikainen, Marko
    Hamalainen, Timo D.
    2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2008, : 157 - 162
  • [47] ADAPTIVE LATTICE FILTER IMPLEMENTATIONS ON PIPELINED MULTIPROCESSOR ARCHITECTURES
    MEYER, MD
    AGRAWAL, DP
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1990, 38 (01) : 122 - 124
  • [48] Multiprocessor architectures for embedded system-on-chip applications
    Ravikumar, CP
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 512 - 519
  • [49] Multiprocessor DSP scheduling in system-on-a-chip architectures
    Gai, P
    Abeni, L
    Buttazzo, G
    EUROMICRO RTS 2002: 14TH EUROMICRO CONFERENCE ON REAL-TIME SYSTEMS, PROCEEDINGS, 2002, : 231 - 238
  • [50] Performances of multiprocessor multidisk architectures for continuous media storage
    Gennart, BA
    Messerli, V
    Hersch, RD
    STORAGE AND RETRIEVAL FOR STILL IMAGE AND VIDEO DATABASES IV, 1996, 2670 : 286 - 299