A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength beta. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its ``loop'' bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the ``loop'' cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75--26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.