Intra level mix and match lithography for sub-100nm CMOS devices using the JBX-9300FS point-electron-beam system

被引：0

作者：

Narihiro, M ^{[1
]}

Wakabayashi, H ^{[1
]}

Ueki, M ^{[1
]}

Arai, K ^{[1
]}

Ogura, T ^{[1
]}

Ochiai, Y ^{[1
]}

Mogami, T ^{[1
]}

机构：

[1] NEC Corp Ltd, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291198, Japan

来源：

关键词：

D O I：

10.1109/IMNC.2000.872678

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：162 / 163

页数：2

共 4 条

[1] Intra-level mix-and-match lithography process for fabricating sub-100-nm complementary metal-oxide-semiconductor devices using the JBX-9300FS point-electron-beam system
Narihiro, Mitsuru
Wakabayashi, Hitoshi
Ueki, Makoto
Arai, Kohichi
Ogura, Takashi
Ochiai, Yukinori
Mogami, Tohru
Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes & Review Papers, 2000, 39 (12): : 6843 - 6848
[2] Intra-level mix-and-match lithography process for fabricating sub-100-nm complementary metal-oxide-semiconductor devices using the JBX-9300FS point-electron-beam system
Narihiro, M
Wakabayashi, H
Ueki, M
Arai, K
Ogura, T
Ochiai, Y
Mogami, T
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (12B): : 6843 - 6848
[3] 100kV high resolution E-Beam Lithography System, JBX-9300FS
Takemura, H
Ohki, H
Isobe, M
PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY IX, 2002, 4754 : 690 - 696
[4] ELECTRON-BEAM DUV INTRA-LEVEL MIX-AND-MATCH LITHOGRAPHY FOR RANDOM LOGIC 0.25-MU-M CMOS
JONCKHEERE, R
TRITCHKOV, A
VANDRIESSCHE, V
VANDENHOVE, L
MICROELECTRONIC ENGINEERING, 1995, 27 (1-4) : 231 - 234