Residual Stress Properties of Nickel and Copper Deposits Used for C4 Interconnects
被引:1
作者:
Arvin, C. L.
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机构:
IBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Arvin, C. L.
[1
]
Scott, G. J.
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h-index: 0
机构:
IBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Scott, G. J.
[1
]
Goldsmith, C. C.
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h-index: 0
机构:
IBM Corp, Syst & Technol Grp, Fishkill, NY 12533 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Goldsmith, C. C.
[2
]
Parks, C.
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h-index: 0
机构:
IBM Corp, Syst & Technol Grp, Fishkill, NY 12533 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Parks, C.
[2
]
Wang, C.
论文数: 0引用数: 0
h-index: 0
机构:
Enthone Inc, West Haven, CT 06516 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Wang, C.
[3
]
Zhang, Y.
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机构:
Enthone Inc, West Haven, CT 06516 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Zhang, Y.
[3
]
Abys, J.
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机构:
Enthone Inc, West Haven, CT 06516 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Abys, J.
[3
]
Takahashi, K. M.
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h-index: 0
机构:
Oxalis Consulting Engineers, Warren, NJ 07059 USAIBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
Takahashi, K. M.
[4
]
机构:
[1] IBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA
[2] IBM Corp, Syst & Technol Grp, Fishkill, NY 12533 USA
[3] Enthone Inc, West Haven, CT 06516 USA
[4] Oxalis Consulting Engineers, Warren, NJ 07059 USA
来源:
SURFACTANT AND ADDITIVE EFFECTS ON THIN FILM DEPOSITION AND PARTICLE GROWTH 2
|
2011年
/
35卷
/
22期
关键词:
D O I:
10.1149/1.3649926
中图分类号:
O646 [电化学、电解、磁化学];
学科分类号:
081704 ;
摘要:
Semiconductor packaging technology requires understanding how the fundamental materials properties of different structures interact to impact the final reliability of the system, how to measure those properties and how to control them. We investigated the impact of residual stress of electrodeposited Ni (sulfamate) and Cu (sulfate and MSA) deposits that are used for C4 (controlled collapse chip connection) interconnects using X-ray lattice distortion method, sin(2)psi and wafer bow measurement as a function of thermal excursions up to 400 degrees C. The impact of this stress on the final reliability of a flip chip package was studied in order to determine useful guidelines to limit post-plate process temperatures, to conduct anneals when possible, to establish best known methods to monitor plated materials stresses and to develop methods to maintain and condition chemical plating baths to control those deposits. Finally, dynamic SIMS was utilized to aid in the interpretation of those data.