Functional testing of RISC-microprocessors

A functional testing procedure based on the functional decomposition of microprocessor models with regard for the specifics of RISC-architecture is described. Conceptual models of RISC-microprocessors are represented as tested objects in the form of block schemes and generalized register transfer graphs. Test methods and stages as well as synthesis of tests for the main mechanisms and functional modules of microprocessors are studied. Special attention is paid to testing of data processing and transfer control units. The high testability of the RISC-architecture is corroborated by the test results.