A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

被引：0
|
作者：
Santos, DM [1 ]
Dow, SF [1 ]
Levi, ME [1 ]
机构：
[1] UNIV AVEIRO,P-3810 AVEIRO,PORTUGAL
来源：
1995 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE RECORD, VOLS 1-3 | 1996年
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D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
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页码：289 / 291
页数：3
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