Timing-constrained redundant via insertion for yield optimization

被引：0

作者：

Yan, Jin-Tai ^{[1
]}

Chiang, Bo-Yi ^{[1
]}

Chen, Zhi-Wei ^{[1
]}

机构：

[1] Chung Hua Univ, Dept Comp Sci & Informat Engn, Hsinchu, Taiwan

来源：

2007 IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

According to the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion the experimental results show that our proposed enhanced two-phase insertion approach only reduces 0.003%similar to 0.005% total wire length and 0.0001%similar to-0.0003% chip yield to maintain 100% timing constraints for the tested benchmarks.

引用

页码：213 / 216

页数：4

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