Multiobjective optimization of VLSI interconnect parameters

被引：10

作者：

Anand, MB ^{[1
]}

Shibata, H

Kakumu, M

机构：

[1] Toshiba Co Ltd, ULSI Proc Engn Lab, Adv Microelect Ctr, Yokohama, Kanagawa 235, Japan

[2] Toshiba Corp, Microprocessor Prod Engn Dept, Micro & Custom LSI Div, Kawasaki, Kanagawa 210, Japan

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1998年 / 17卷 / 12期

关键词：

integrated circuit design; integrated circuit interconnections; integrated circuit modeling; optimization methods;

D O I：

10.1109/43.736565

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The significant role played by interconnects in determining the speed and chip size of very-large-scale integrated circuits (VLSI's) necessitates the development of new processes and tools for almost every device generation. Since such development usually requires lead times of several years, it has become essential to know, several years in advance, the various interconnect parameters for a particular generation. In this paper, a tool for optimizing interconnect parameters is presented. The formulation of an optimization problem that can be solved using standard algorithms is shown to be possible, and the optimization results obtained for future device generations are discussed. These results can be used to construct an interconnect technology roadmap, Last, shortcomings of and possible improvements to existing system-level critical path models are discussed.

引用

页码：1252 / 1261

页数：10

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