During the design and implementation of digital circuits for various applications, mapping of algorithms to different hardware components is a central task to achieve best in class performance (e.g., low power consumption per position fix, position accuracy and position deviation for satellite navigation receivers). During the last decade software defined radio receivers (SDRs) and Field Programmable Gate Array (FPGA) based receivers gain more and more importance during the prototyping phase and for receivers with an expected low volume production. These receivers are also of special interest during the introduction of new signals and frequency bands. FPGA based receivers allow a flexible design and the implementation of highly parallel digital logic and software based processing at the same time. The fundamental drawback of FPGA based GNSS receiver solutions is the high design complexity and the enlarged design space. In this context the design space describes the number of parameters the designer has to consider, to optimize the final design for a given application. Successful navigation in this design space, requires experience in various disciplines (e.g. Radio Frequency (RF) engineering, signal processing, GNSS algorithm design). The main idea of this paper is to ease the design, simulation and cost optimization of Software Defined Radio (SDR) GNSS receivers, implemented on standard PCs, Graphical Processing Units (GPUs) and FPGAs. The idea is to describe the receiver architecture and the receiver specifications at a very high and thus understandable level. During the next step a compiler maps the different receiver signal processing blocks to the existing hardware (i.e. General Purpose Computer (GPC), FPGA or GPU). Using this approach, the most time consuming parts (i.e. design description and specification) have to be done only once and the design is based on a single code base.
