Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu2O3 gate dielectrics

被引：24

作者：

Yen, Li-Chen ^{[1
]}

Hu, Chia-Wei ^{[2
]}

Chiang, Tsung-Yu ^{[1
]}

Chao, Tien-Sheng ^{[1
]}

Pan, Tung-Ming ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Dept Electrophys, Hsinchu 30010, Taiwan

[2] Chang Gung Univ, Dept Elect Engn, Tao Yuan 333, Taiwan

来源：

APPLIED PHYSICS LETTERS | 2012年 / 100卷 / 17期

关键词：

HIGH-PERFORMANCE; TFTS; STACK;

D O I：

10.1063/1.4705472

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3 gate dielectric. High-kappa Eu2O3 LTPS-TFT annealed at 500 degrees C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm(2)/V-s, a small subthreshold swing of 142 mV/decade, and a high I-on/I-off current ratio of 1.34 x 10(7). These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4705472]

引用

页数：3

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