Impact of Common Source Inductance on the Gate-Source Voltage Negative Spike of SiC MOSFET in Phase-Leg Configuration

被引：3
作者：
Shao, Tiancong [1 ]
Li, Zhijun [1 ]
Zheng, Trillion Q. [1 ]
Li, Hong [1 ]
Huang, Bo [2 ]
Wang, Zuoxing [1 ]
Zhang, Zhipeng [1 ]
机构：
[1] Beijing Jiaotong Univ, Sch Elect Engn, Beijing, Peoples R China
[2] Global Power Technol Co Ltd, Beijing, Peoples R China
来源：
2020 IEEE 9TH INTERNATIONAL POWER ELECTRONICS AND MOTION CONTROL CONFERENCE (IPEMC2020-ECCE ASIA) | 2020年
基金：
中国国家自然科学基金;
关键词：
common source inductance; negative voltage spike; phase-leg configuration; SiC MOSFET; SUPPRESSION; DEVICES;
D O I：
10.1109/IPEMC-ECCEAsia48364.2020.9368245
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The cross-talk and coupling effect between SiC MOSFETs in the phase-leg configuration limits the further release of SiC MOSFET performance in applications. A significant negative voltage spike on the gate-source voltage of SiC MOSFET will breakdown the device, even deteriorate peculiarities in threshold voltage variation and further impact the lifetime. In consideration of the common source inductance, the negative spike of SiC MOSFETs gate-source voltage still needs mechanism research. This paper reveals the dynamic underdamped mechanism to explain the impact of common source inductance on the gate-source voltage negative spike of SiC MOSFET in phase-leg configuration. Experimental results verify this dynamic underdamped mechanism based on the experimental comparison of 3-pin and 4-pin packaged SiC MOSFETs.
引用
收藏
页码：3361 / 3365
页数：5
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