A serial 10 Gigabit Ethernet transceiver on digital 0.13um CMOS

被引：0
|
作者：
Wu, B [1 ]
Sutu, YH [1 ]
Ramamurthy, K [1 ]
Zheng, D [1 ]
Cheung, E [1 ]
Tran, T [1 ]
Jiang, Y [1 ]
Rana, M [1 ]
机构：
[1] BitBlitz Commun Inc, Milpitas, CA 95035 USA
来源：
ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a serial 10 Gigabit Ethernet transceiver IC. To the extent of our knowledge, this is the first report of such a device on bulk CMOS. It uses a novel analog phase rotator in each of the 5 Clock-and-Data Recovery (CDR) units for an efficient implementation of multi-channel receiver circuits. A substantial amount of digital logic is present on the chip to perform the encoding, decoding, FIFO, MDIO etc. functions as specified by the 802.3ae standard. Sub-picosecond RMS jitter is nevertheless achieved in such a hostile environment. The chip is implemented in a 0.13um digital CMOS process and dissipates 1.5 Watts under a 1.5-volt power supply.
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收藏
页码：197 / 200
页数：4
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