Processor modeling for hardware software codesign

被引：12

作者：

Rajesh, V ^{[1
]}

Moona, R ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Comp Engn & Sci, Cadence Res Ctr, Kanpur 208016, Uttar Pradesh, India

来源：

TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/ICVD.1999.745137

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In hardware are - software codesign paradigm often a performance estimation of the system is needed for hardware are - software partitioning. The tremendous growth of application specific embedded systems necessitate high level system design tools for rapid prototyping. This work involves design of a language Sim-nML,which will be the base for a high level system design environment. The language is simple, elegant and powerful enough to express the behavior of the processor at instruction level. This language is used as the base for a whole set of tools such as assembler; disassembler and simulator generator: As a pall of this,cork, Ire implemented an instruction set simulator generator which takes Sim-nML description of the processor as input and produces C++ code for performance simulator I the envisage the use of the generated simulator for cycle based analysis of the processor and for performance estimation of the system. This work is primarily an extension of nML[2] language.

引用

页码：132 / 137

页数：6

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