A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug

被引：5

作者：

Cao, Yuting ^{[1
]}

Zheng, Hao ^{[1
]}

Palombo, Hernan ^{[1
]}

Ray, Sandip ^{[2
]}

Yang, Jin ^{[3
]}

机构：

[1] Univ S Florida, CSE, Tampa, FL 33620 USA

[2] NXP Semicond, Austin, TX USA

[3] Intel, Strateg CAD Lab, Hillsboro, OR USA

来源：

2017 IEEE 35TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD) | 2017年

关键词：

SIGNAL SELECTION;

D O I：

10.1109/ICCD.2017.35

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Reconstructing system-level behavior from silicon traces is a critical problem in post-silicon validation of System-on-Chip designs. Current industrial practice in this area is primarily manual, depending on collaborative insights of the architects, designers, and validators. This paper presents a trace analysis approach that exploits architectural models of system-level protocols to reconstruct design behavior from partially observed silicon traces in the presence of ambiguous and noisy data. The output of the approach is a set of all potential interpretations of a system's internal execution abstracted to system-level protocols. To support the trace analysis approach, a companion trace signal selection framework guided by system-level protocols is also presented, and its impacts on the complexity and accuracy of the analysis approach are discussed. That approach and the framework have been evaluated on a multi-core System-on-Chip prototype that implements a set of common industrial system-level protocols.

引用

页码：177 / 184

页数：8

共 8 条

[1] Formal-Analysis-Based Trace Computation for Post-Silicon Debug
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Wilton, Steven J. E.
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (11) : 1997 - 2010
[2] WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip
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[3] Layout-aware Selection of Trace Signals for Post-Silicon Debug
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[4] Scalable Signal Selection for Post-Silicon Debug
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Wilton, Steven J. E.
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[5] On Evaluating Signal Selection Algorithms for Post-Silicon Debug
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Wilton, Steven J. E.
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[6] Application Level Hardware Tracing for Scaling Post-Silicon Debug
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de Paula, Flavio M.
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[7] Feature-Based Signal Selection for Post-Silicon Debug Using Machine Learning
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[8] Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation
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