Design of high speed ternary full adder and three-input XOR circuits using CNTFETs

This paper proposes a new high speed ternary full adder (TFA) cell for carbon nano tube field effect transistor (CNTFET) technology. The proposed design has a symmetric pull-up and pull-down networks along with a resistive voltage divider as its integral part, which is configured using transistors. The design takes inputs through a decoding unit and uses ternary nature of A & B but inherent binary nature of Cin leading to simplicity in design. The design demonstrates high driving power and robustness in terms of insusceptibility to voltage and temperature variations. The sum generation unit of proposed design is further modified for achieving an energy efficient three-input ternary XOR circuit which can be used as a basic cell in modern circuit design. Hspice simulation results with 32nm Stanford CNTFET model show 49% reduction in delay with 19% progress in power-delay product (PDP) for the proposed TFA and 43% reduction in delay with 48 % improvement in PDP for the proposed three input ternary XOR circuit in comparison with the CNTFET-based designs, recently published in the literature.