Test structures for the evaluation of 3D chip interconnection schemes

被引：1

作者：

Mathewson, A. ^{[1
]}

Brun, J. ^{[2
]}

Franiatte, R. ^{[2
]}

Nowodzinski, A. ^{[2
]}

Ancient, R. ^{[2
]}

Sillon, N. ^{[2
]}

Depoutot, F. ^{[3
]}

Dubois-Bonvalot, B. ^{[3
]}

机构：

[1] Tyndall Natl Inst, Cork, Ireland

[2] CEA, F-38050 Grenoble, France

[3] Hardware Secur Res Grp Gemalto, F-38050 Grenoble, France

来源：

2008 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, CONFERENCE PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/ICMTS.2008.4509325

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper a test structure is described which facilitates the evaluation of interconnection schemes for chip on wafer attachment and interconnection. Microinsert technology is described and some of the characterization that the test structure permits is discussed Thermal cycling experiments were performed on this test structure and although the resistance of the contact chain seemed not to change as a function of number of cycles, detailed investigation revealed that the metal resistance was reducing while contact resistance was increasing and the two effects were trading off against each other. Possible explanations for this behavior have been provided.

引用

页码：117 / +

页数：2

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